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NJU8752
PRELIMINARY
Analog Signal Input Class D Amplifier for Piezo Speaker
! GENERAL DESCRIPTION
The NJU8752 is an analog signal input monaural class D amplifier for Piezo speaker. The NJU8752 includes Inversion operational amplifier input circuit, PWM modulator, an output-short protector and a low voltage detector. Input part operates on 3.3V(TYP) as power supply and Output part operates up to 16.0V(MAX). Therefore, it drives Piezo speaker with louder sound and High efficiency. The NJU8752 incorporates BTL amplifier, which eliminate AC coupling capacitors, capable of driving Piezo speaker with simple external LC low-pass filters. Class D operation achieves lower power operation for Piezo speaker, thus the NJU8752 is suited for battery powered applications.
! PACKAGE OUTLINE
NJU8752V
! FEATURES
Piezo Speaker Driving 1-channel Analog Signal Input, 1-channel BTL Output Standby(Hi-Z), Mute Control Built-in Low Voltage Detector Built-in Short Protector Operating Voltage 2.7 ~ 3.6V (Input) 6.0 ~ 16.0V (Output) # C-MOS Technology # Package Outline SSOP14 # # # # # #
! PIN CONFIGURATION
VDD IN TEST 1 MUTE VSS OUTP VDDO 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VSS COM TEST 2 STBY VSS OUTN VDDO
! BLOCK DIAGRAM
VDD VSS VDDO IN + COM +
Pulse Width Modulator
OUTP VSS VDDO OUTN VSS
Short Protector
Soft Start
Control
Logic
Low Voltage Detector
MUTE
TEST 1 STBY TEST 2
Ver.2003-05-29
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NJU8752
! PIN DESCRIPTION
Function Power Supply: VDD=3.3V Signal Input Maker test 1 3 TEST 1 I This pin must be connected to GND. Mute Control 4 MUTE I Low : Mute ON High : Mute OFF 5, 10,14 VSS - Power GND: VSS=0V 6 OUTP O Positive Output 7, 8 VDDO - Output Power Supply : VDDO=16.0V max. 9 OUTN O Negative Output Standby Control 11 STBY I Low : Standby ON High : Standby OFF Maker test 2 12 TEST 2 I This pin must be connected to GND. 13 COM - Analog common *Pin No. 5(VSS),10(VSS) and 14(VSS) should be connected at a nearest point to the IC. *Pin No. 7(VDDO) and 8(VDDO) should be connected at a nearest point to the IC. *Pin No. 4(MUTE) and 11(STBY) must be connected to VDD, when these pins are not used. No. 1 2 SYMBOL VDD IN I/O - I
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Ver.2003-05-29
NJU8752 NJU3555
! FUNCTIONAL DESCRIPTION
(1) Signal Output The OUTP and OUTN generate PWM output signals, which will be converted to analog signal via external 2nd-order or higher LC filter. A switching regulator with a high response against a voltage fluctuation is the best selection for the VDDO, which are the power supply for output drivers. To obtain better THD performance, the stabilization of the power is required. (2) Standby By setting the STBY pin to "L", the standby mode is enabled. In the standby mode, the entire functions of the NJU8752 enter a low-power state, and the output pins (OUTP and OUTN) are high impedance. (3) Mute By setting the MUTE pin to "L", the Mute function is enabled. In the Mute mode, the output pins (OUTP and OUTN) output square wave (Duty: 50%). (4) Low Voltage Detector When the power supply voltage drops down to below VDD (MIN), the internal oscillation is halted for prevention to generate unwanted frequency, and the output pins (OUTP and OUTN) become in high impedance. (5) Short Circuit Protection The short protector, which protects the NJU8752 against high short-circuit current, turns off the output driver. After about 5 seconds from the protection, the NJU8752 returns to normal operation. The short protector functions at the following accidents.
* Short * Short * Short
between OUTP and OUTN between OUTP and VSS between OUTN and VSS
Note 1) The detectable current and the period for the protection depend on the power supply voltage and ambient temperature. Note 2) The short protector is not effective for a long term short-circuit but for an instantaneous accident. Continuous high-current may cause permanent damage to the NJU8752.
Ver.2003-05-29
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NJU8752
! ABSOLUTE MAXIMUM RATINGS
(Ta=25C) PARAMETER Supply Voltage Input Voltage Operating Temperature Storage Temperature Power Dissipation SSOP14 SYMBOL VDD VDDO Vin Topr Tstg PD RATING -0.3 ~ +4.0 -0.3 ~ +18.0 -0.3 ~ VDD+0.3 -40 ~ +85 -40 ~ +125 300 UNIT V V V C C mW
Note 1) All voltage are relative to "VSS =0V" reference. Note 2) The LSI must be used inside of the "Absolute maximum ratings". Otherwise, a stress may cause permanent damage to the LSI. Note 3) De-coupling capacitors for VDD(Pin 1)-VSS(Pin 14), VDDO(Pin 7)-VSS(Pin 5) and VDDO(Pin 8)-VSS(Pin 10) should be connected for stable operation.
! ELECTRICAL CHARACTERISTICS
(Ta=25C, VDD=3.3V, VDDO=12.0V, VSS=0V, Input Signal=1kHz, Input Signal Level=200mVrms, Frequency Band=20Hz~20kHz, Load Impedance=0.8F, 2nd-order 34kHz LC Filter(Q=0.75)) PARAMETER VDD Supply Voltage VDDO Supply Voltage Input Impedance Voltage Gain Output THD Maximum Output S/N Dynamic Range Maximum Mute Attenuation Operating Current(Stanby) Operating Current (No signal input) Input Voltage Input Leakage Current SYMBOL VDD VDDO ZIN AV THD Vo SN Drange MAT IST IDD VIH VIL ILK CONDITIONS MIN 2.7 6.0 7 90 0.7VDD 0 TYP 3.3 12.0 20 31 0.05 10 80 83 3.5 MAX 3.6 16.0 0.08 1 10 VDD 0.3VDD 1.0 UNIT V V k dB % Vrms dB dB dB A mA V V A Note
IN pin Input Signal Level =200mVrms Output THD=10% A weight A weight
4 4 4
No-load operating No Signal Input MUTE, STBY pins MUTE, STBY pins MUTE, STBY pins
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Ver.2003-05-29
NJU8752 NJU3555
Note 4) Test system of the output THD, S/N and Dynamic Range The output THD, S/N and dynamic range are tested in the system shown in Figure 1, where a 2nd-order LC LPF and another filter incorporated in an audio analyzer are used.
Input Signal
NJU8752
2nd-order LC LPF
Filter 20kHz (AES17)
THD Measuring Apparatus
NJU8752 Test Board
Audio Analyzer
Figure 1. Output THD, S/N and Dynamic Range Test System
2nd-order LPF Filters
: Refer to "Typical Application Circuit". : 22Hz HPF + 20kHz LPF(AES17) (with the A-Weight filter for S/N and Dynamic-range tests)
Ver.2003-05-29
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NJU8752
! TYPICAL APPLICATION CIRCUIT
*LLB2520 is manufactured by TOKO, INC. For detail information, please refer its technical papers. LLB2520 33~47H 0.1F 5~10 LLB2520 33~47H 0.5~2F 0.1F
VDD
10F 0.1F
5~10
VDD(1) VSS(14)
OUTP(6)
Piezo Speaker
IN
0.01F
IN(2) COM(13)
10F
NJU8752
3.3k
2.2F
OUTN(9) VDDO(7) VSS(5)
0.1F
10F
VDDO
MUTE(4) STBY(11) TEST1(3)
VDDO(8) VSS(10)
0.1F
10F
VDDO
TEST2(12)
Figure 2. Application Circuit example
Note 5) De-coupling capacitors must be connected between each power supply pin and GND. The capacity value should be adjusted on the application circuit and the operation temperature. It may malfunction if capacity value is small. Note 6) The power supply for VDDO require fast driving response performance such as a switching regulator for better THD. THD performance becomes worse by ripple if the capacity of De-coupling capacitors is small. Note 7) The above circuit shows only application example and does not guarantee the any electrical characteristics. Therefore, please test the circuit carefully to fit your application. The cutoff frequency of the LC filter influences the quality of sound. The Q factor of the LC filter must be less than "1". Otherwise, the operating current increase when the frequency of input signal is closed to the cutoff frequency. Note 8) The transition time for MUTE and STBY signals must be less than 100s. Otherwise, a malfunction may be occurred. Note 9) (1)-(14) indicates pin number.
[CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.
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Ver.2003-05-29

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